FanoCore™ Ultra-High Density Fan-Out Wafer-Level Packaging Platform

FanoCore™ Ultra-HD Fan-Out WLP – Next-Generation Fan-Out Wafer-Level Packaging Solution for 2.5D/3D Heterogeneous Integration

FanoCore™ adopts fifth-generation redistribution layer (RDL) technology with 2 µm/2 µm line width/spacing and embedded multi-die interconnect bridge (EMIB) architecture, achieving ≤0.8 mm package thickness and >1 Tb/s·mm edge bandwidth on 12-inch reconstituted wafers. This provides a high-yield, low-warpage, low-cost heterogeneous integration solution for mobile SoCs, HPC, automotive, and RF devices.

YCHIPWAY

Product dimensions：5.0×5.0mm ~ 80×80mm, supporting 2.5D/3D stacking, suitable for ultra-large size and ultra-high I/O density heterogeneous integrated packaging

Product Application：High-end AI computing chips, server CPUs/GPUs, FPGAs, 5G base station chips, automotive high-computing chips, aerospace core devices

detailed introduction

Product Overview

The FanoCore™ platform reconstructs wafers by embedding chips into molding compound first, then fabricating multilayer fine RDLs on the wafer surface to achieve I/O fan-out without traditional substrates. The platform supports package sizes up to 40 mm × 40 mm, 2/3/4-layer RDL stacking, and backside RDL processes. It enables multi-chip integration, passive components, silicon capacitors, and TSV-less high-frequency interconnects on the same reconstituted wafer, delivering "wafer-level packaging + 2.5D performance" convergence.

Applications

• Mobile & Wearables: Flagship APs, PMICs, RF FEM modules

• High-Performance Computing: GPU/CPU + HBM integration, Chiplet-based heterogeneous SoCs

• Automotive Electronics: 77 GHz radar SoCs, onboard AI accelerators

• RF & Millimeter-Wave: AiP antenna modules, 5G/6G base station transceivers

Technical Features

Ultra-High-Density RDL: 2 µm/2 µm L/S, 12 µm micro-bump pitch, supporting 8,000+ I/Os

Low Warpage Control: Stress-balanced stackup + molding compound formulation, warpage < 80 µm@300 mm

Thermal/Electrical Co-Design: >200 W thermal design power path, 8 µm RDL copper thickness to reduce IR drop

Reliability Standards: JEDEC J-STD-020 MSL-3 compliant, -55°C ~ 150°C 1,000-cycle TC, uHAST 96 h

Manufacturing Scale: 12-inch mass production line, >60k wafers/month capacity, >98% yield

UCIe/BoW Interface Compatibility: Seamless Chiplet ecosystem integration, Die-to-Die <0.5 pJ/bit

FanoCore™ empowers system-level innovation with wafer-scale precision, offering optimal trade-offs in size, performance, cost, and reliability for customers.

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