LingChip Heterogeneous Integration Platform

Product Overview

The Lingxin® Heterogeneous Integration Platform consists of four core modules: Chiplet Library, Interconnect Framework, Packaging Process, and Design Toolchain:

Chiplet Library: Covers 7 nm high-performance computing chiplets, 16 nm AI acceleration chiplets, 28 nm I/O interface chiplets, 22 nm automotive-grade security chiplets, and HBM3E/HBM-PIM memory chiplets, all silicon-verified.

Interconnect Framework: Compatible with UCIe/BoW/OpenHBI protocols, supports 8–32 GT/s high-speed interconnects, and offers CXL 3.0 cache-coherent expansion.

Packaging Process: Supports CoWoS-S/R, InFO-PoP, Hybrid Bonding (10 μm pitch), integrates TSVs and micro-bumps, with signal integrity <0.4 dB/mm@32 Gbps.

Design Toolchain: Provides Die-to-Die PHY/controller IP, SI/PI co-simulation, thermal-mechanical joint simulation, DFT/DFM rule checks, and supports full Cadence/Synopsys workflows.

Applications

• Data center CPUs/GPUs, AI training/inference accelerators

• Automotive high-performance domain controllers, central computing platforms

• 5G+6G base stations, edge servers

• Industrial vision, medical imaging, aerospace high-reliability computing

Technical Features

Process Flexibility: Supports hybrid integration of 2/3/4/5 nm logic nodes with mature nodes.

High Bandwidth & Low Latency: Die-to-Die links achieve up to 1 TB/s bandwidth with <4 ns latency.

Low Power Consumption: Utilizes low-swing (0.4 V) signaling and adaptive clock gating, with power efficiency ≥5 pJ/bit.

High Yield: Implements Known Good Die (KGD) strategy for system yield >95%.

Scalable Security: Integrates AES-256/Chinese SM9 security chiplets, supports runtime-reconfigurable security islands.

Fast Time-to-Market: Offers system-level reference designs, SDKs, and thermal/power integrity solutions, enabling customers to achieve mass production within an average of 12 months.